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never stop thinking. hys64t32000[g /h]dl?[3.7/5]?a hys64t64020[g /h]dl?[3.7/5]?a hys64t128021[g /h]dl?[3.7/5]?a 200-pin small outline dual-in-line memory module so-dimm ddr2 sdram data sheet, rev. 0.91, june 2004 memory products
edition 2004-06 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hys64t32000[g /h]dl?[3.7/5]?a hys64t64020[g /h]dl?[3.7/5]?a hys64t128021[g/ h]dl?[3.7/5]?a 200-pin small outline dual-in-line memory module so-dimm ddr2 sdram data sheet, rev. 0.91, june 2004 memory products
template: mp_a4_v2.2_2003-10-07.fm all hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a revision history: rev. 0.91 2004-06 previous revision: rev. 0.83 2003-09 page subjects (major changes since last revision) all editorial changes all removed hys64t128022hdl products and all -3 products all added hys64t128021[g/]dl products we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram data sheet 5 rev. 0.91, 2004-06 09122003-ftxn-km26 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2blockdiagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 i dd test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 odt (on die termination) current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 electrical characteristics & ac timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 product type nomenclature (ddr2 drams and dimms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table of contents
200-pin small outline dual-in-line memory module ddr2 sdram hys64t32000[g/h]dl?[3.7/5]?a hys64t64020[g/h]dl?[3.7/5]?a hys64t128021[g/h]dl?[3.7/5]?a data sheet 6 rev. 0.91, 2004-06 09122003-ftxn-km26 1 overview this chapter gives an overview of the 1.8 v 200-pin small outline dual-in-line memory module, 256 mbyte and 512 mbyte and describes its main characteristics. 1.1 features 200-pin non-ecc unbuffered 8-byte dual-in-line ddr2 sdram module for notebooks and other application where small form factors are required. one rank 32m 64, two ranks 64m 64 and 128m 64 module organisation and 32m 16 and 64m 8 chip organisation jedec standard double-data-rate-two synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply 256 ,512 mbyte and 1gbyte modules built with 512mb ddr2 sdrams in 60-ball fbga (p?tfbga?60) and 84-ball fbga (p?tfbga?84) chipsize packages programmable cas latencies (3, 4 and 5), burst length (4 & 8) and burst type auto refresh (cbr) and self refresh all inputs and outputs sstl_1.8 compatible off-chip driver impedance adjustment(ocd) and on-die termination(odt) serial presence detect with e 2 prom low profile modules form factor: 67.60 mm x 30.00 mm (mo-224) based on jedec standard reference layouts raw card ?a?, ?c? and ?d? 1.2 description the infineon hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a module family are low profile so-dimm modules with 30,0 mm height based on ddr2 technology. dimms are available as non-ecc modules in 32m 64 (256 mbyte),64m 64 (512 mbyte) and 128m 64 (1 gbyte) organisation and density, intended for mounting into 200-pin connector sockets. the memory array is designed with 512mb double- data-rate-two (ddr2) synchronous drams. decoupling capacitors are mounted on the pcb board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are available to the customer. table 1 performance product type speed code ?3.7 ?5 units speed grade pc2?4200 4?4?4 pc2?3200 3?3?3 ? max. clock frequency @cl5 f ck5 266 200 mhz @cl4 f ck4 266 200 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 15 15 ns min. row precharge time t rp 15 15 ns min. row active time t ras 45 40 ns min. row cycle time t rc 60 55 ns
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 7 rev. 0.91, 2004-06 09122003-ftxn-km26 note: the compliance code is printed on the module label and describes the speed grade,e.g. "512mb 2r 16 pc2?3200s?33310?a" where "512mb" tells the density in megabytes, "2rx16" means 2 ranks on module built of 16 components, "pc2?3200s" means ddr2 so-dimm with 4.26 gb/s module bandwidth and "444- 11" means cas latency of 4, rcd 1) latency of 4, and rp 2) latency of 4 using jedec spd revision 1.0. all part numbers end with a place code, designating the silicon die revision. example: hys64t32000gdl?3.7? a, indicating rev. a dice are used for ddr2 sdram components. for all infineon ddr2 module and component nomenclature see chapter 8 of this datasheet. table 2 ordering information product type compliance code description sdram technology hys64t32000gdl?3.7?a pc2?4200s?444?10?c0 one rank 256 mbyte so?dimm 512 mbit ( 16) hys64t64020gdl?3.7?a pc2?4200s?444?10?a0 two ranks 512 mbyte so?dimm 512 mbit ( 16) hys64t128021gdl?3.7?a pc2?4200s?444?10?d0 two ranks 1 gbyte so?dimm 512 mbit ( 8) hys64t32000gdl?5?a pc2?3200s?333?10?c0 one rank 256 mbyte so?dimm 512 mbit ( 16) hys64t64020gdl?5?a pc2?3200s?333?10?a0 two ranks 512 mbyte so?dimm 512 mbit ( 16) hys64t128021gdl?5?a pc2?3200s?333?10?d0 two ranks 1 gbyte so?dimm 512 mbit ( 8) hys64t32000hdl?3.7?a pc2?4200s?444?10?c0 one rank 256 mbyte so?dimm 512 mbit ( 16) hys64t64020hdl?3.7?a pc2?4200s?444?10?a0 two ranks 512 mbyte so?dimm 512 mbit ( 16) hys64t128021hdl?3.7?a pc2?4200s?444?10?d0 two ranks 1 gbyte so?dimm 512 mbit ( 8) hys64t32000hdl?5?a pc2?3200s?333?10?c0 one rank 256 mbyte so?dimm 512 mbit ( 16) hys64t64020hdl?5?a pc2?3200s?333?10?a0 two ranks 512 mbyte so?dimm 512 mbit ( 16) hys64t128021hdl?5?a pc2?3200s?333?10?d0 two ranks 1 gbyte so?dimm 512 mbit ( 8) 1) rcd: row column delay 2) rp: row precharge table 3 address format dimm density module organization memory ranks # of sdrams # of row/bank/column bits raw card 256 mb 32m 64 1 4 13/2/10 c 512 mb 64m 64 2 8 13/2/10 a 1gb 128m 64 2 16 14/2/10 d
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 8 rev. 0.91, 2004-06 09122003-ftxn-km26 1.3 pin configuration the pin configuration of the small outline ddr2 sdram dimm is listed by function in table 5 (200 pins). the abbreviations used in columns pin and buffer type are explained in table 6 and table 7 respectively. the pin numbering is depicted in figure 1 table 4 components on modules 1) 1) for a detailed description of all functionalities of the dram components on these modules see the component data sheet. product type dram components dra m density dram organisation hys64t32000gdl hyb18t512160ac 512 mbit 32m 16 hys64t64020gdl hys64t32000hdl 2) hyb18t512160af 2) 2) green product 512 mbit 32m 16 hys64t64020hdl 2) hys64t128021gdl hyb18t512800ac 512 mbit 64m 8 hys64t128021hdl 2) hyb18t512800af 2) 512 mbit 64m 8 table 5 pin configuration of so-dimm pin# name pin type buffer type function clock signals 30 ck0 i sstl clock signals 2:0 164 ck1 i sstl 32 ck0 isstl complement clock signals 2:0 166 ck1 isstl 79 cke0 i sstl clock enable rank 0 80 cke1 i sstl clock enable rank 1 note: 2-rank module nc nc ? note: 1-rank module control signals 110 s0 isstl chip select rank 0 115 s1 isstl chip select rank 1 note: 2-rank module nc nc ? note: 1-rank module 108 ras isstl row address strobe 113 cas isstl column address strobe 109 we isstl write enable address signals 107 ba0 i sstl bank address bus 1:0 106 ba1 i sstl 102 a0 i sstl address bus 4:0 101 a1 i sstl 100 a2 i sstl 99 a3 i sstl 98 a4 i sstl
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 9 rev. 0.91, 2004-06 09122003-ftxn-km26 97 a5 i sstl address bus 11:5 94 a6 i sstl 92 a7 i sstl 93 a8 i sstl 91 a9 i sstl 105 a10 i sstl ap i sstl 90 a11 i sstl 89 a12 i sstl address signal 12 116 a13 i sstl address signal 13 note: 512m 4/8 nc nc ? note: module based on 512 mbit 16 data signals 5 dq0 i/o sstl data bus 26:0 7 dq1 i/o sstl 17 dq2 i/o sstl 19 dq3 i/o sstl 4 dq4 i/o sstl 6 dq5 i/o sstl 14 dq6 i/o sstl 16 dq7 i/o sstl 23 dq8 i/o sstl 25 dq9 i/o sstl 35 dq10 i/o sstl 37 dq11 i/o sstl 20 dq12 i/o sstl 22 dq13 i/o sstl 36 dq14 i/o sstl 38 dq15 i/o sstl 43 dq16 i/o sstl 45 dq17 i/o sstl 55 dq18 i/o sstl 57 dq19 i/o sstl 44 dq20 i/o sstl 46 dq21 i/o sstl 56 dq22 i/o sstl 58 dq23 i/o sstl 61 dq24 i/o sstl 63 dq25 i/o sstl 73 dq26 i/o sstl table 5 pin configuration of so-dimm (cont?d) pin# name pin type buffer type function
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 10 rev. 0.91, 2004-06 09122003-ftxn-km26 75 dq27 i/o sstl data bus 63:27 62 dq28 i/o sstl 64 dq29 i/o sstl 74 dq30 i/o sstl 76 dq31 i/o sstl 123 dq32 i/o sstl 125 dq33 i/o sstl 135 dq34 i/o sstl 137 dq35 i/o sstl 124 dq36 i/o sstl 126 dq37 i/o sstl 134 dq38 i/o sstl 136 dq39 i/o sstl 141 dq40 i/o sstl 143 dq41 i/o sstl 151 dq42 i/o sstl 153 dq43 i/o sstl 140 dq44 i/o sstl 142 dq45 i/o sstl 152 dq46 i/o sstl 154 dq47 i/o sstl 157 dq48 i/o sstl 159 dq49 i/o sstl 173 dq50 i/o sstl 175 dq51 i/o sstl 158 dq52 i/o sstl 160 dq53 i/o sstl 174 dq54 i/o sstl 176 dq55 i/o sstl 179 dq56 i/o sstl 181 dq57 i/o sstl 189 dq58 i/o sstl 191 dq59 i/o sstl 180 dq60 i/o sstl 182 dq61 i/o sstl 192 dq62 i/o sstl 194 dq63 i/o sstl data strobe signals table 5 pin configuration of so-dimm (cont?d) pin# name pin type buffer type function
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 11 rev. 0.91, 2004-06 09122003-ftxn-km26 13 dqs0 i/o sstl data strobe bus 7:0 note: see block diagram for corresponding dq signals 31 dqs1 i/o sstl 51 dqs2 i/o sstl 70 dqs3 i/o sstl 131 dqs4 i/o sstl 148 dqs5 i/o sstl 169 dqs6 i/o sstl 188 dqs7 i/o sstl 11 dqs0 i/o sstl complement data strobe bus 7:0 note: see block diagram for corresponding dq signals 29 dqs1 i/o sstl 49 dqs2 i/o sstl 68 dqs3 i/o sstl 129 dqs4 i/o sstl 146 dqs5 i/o sstl 167 dqs6 i/o sstl 186 dqs7 i/o sstl data mask signals 10 dm0 i sstl data mask bus 7:0 26 dm1 i sstl 52 dm2 i sstl 67 dm3 i sstl 130 dm4 i sstl 147 dm5 i sstl 170 dm6 i sstl 185 dm7 i sstl eeprom 197 scl i cmos serial bus clock 195 sda i/o od serial bus data 198 sa0 i cmos slave address select bus 2:0 200 sa1 i cmos power supplies 1 v ref ai ? i/o reference voltage 199 v ddspd pwr ? eeprom power supply 81,82,87,88,95,96,103,104, 111,112,117,118 v dd pwr ? power supply 2,3,8,9,12,15,18,21,24,27,28, 33,34,39,40,41,42,47,48,53, 54,59,60,65,66,71,72,77,78, 121,122,127,128,132,133,138, 139,144,145,149,150,155,156, 161,162,165,168,171,172,177, 178,183,184,187,190,193,196 v ss gnd ? ground plane table 5 pin configuration of so-dimm (cont?d) pin# name pin type buffer type function
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 12 rev. 0.91, 2004-06 09122003-ftxn-km26 other pins 114 odt0 on-die termination control 0 119 odt1 on-die termination control 1 note: 1 rank modules nc 50,69,83,84,85,120,163 nc nc ? not connected note: pins not connected on infineon so-dimms table 6 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 7 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. table 5 pin configuration of so-dimm (cont?d) pin# name pin type buffer type function
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 13 rev. 0.91, 2004-06 09122003-ftxn-km26 figure 1 pin configurat ion so-dimm (200 pin) mppt0140 pin 002 pin 006 pin 010 pin 014 pin 018 pin 022 pin 026 pin 030 pin 034 pin 038 - - - - - - - - - - pin 004 pin 008 pin 012 pin 016 pin 020 pin 024 pin 028 pin 032 pin 036 pin 040 - - - - - - - - - - v ss dq5 dm0 dq6 v ss dq13 dm1 ck0 v ss dq15 v ss v ss dq7 dq12 v ss v ss ck0 dq14 v ss pin 044 pin 048 pin 052 pin 056 pin 060 pin 064 pin 068 pin 072 pin 076 pin 080 pin 084 pin 088 pin 092 pin 096 pin 100 pin 104 pin 108 pin 112 pin 116 pin 120 pin 124 pin 128 pin 132 pin 136 pin 140 pin 144 pin 148 pin 152 pin 156 pin 160 pin 164 pin 168 pin 172 pin 176 pin 180 pin 184 pin 188 pin 192 pin 196 pin 200 dq20 v ss dm2 dq22 v ss dq29 dqs3 v ss dq31 nc/cke1 nc v dd a7 v dd a2 v dd ras v dd a13 nc dq36 v ss v ss dq39 dq44 v ss dqs5 dq46 v ss dq53 ck1 v ss v ss dq55 dq60 v ss dqs7 dq62 v ss sa1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 042 pin 046 pin 050 pin 054 pin 058 pin 062 pin 066 pin 070 pin 074 pin 078 pin 082 pin 086 pin 090 pin 094 pin 098 pin 102 pin 106 pin 110 pin 114 pin 118 pin 122 pin 126 pin 130 pin 134 pin 138 pin 142 pin 146 pin 150 pin 154 pin 158 pin 162 pin 166 pin 170 pin 174 pin 178 pin 182 pin 186 pin 190 pin 194 pin 198 v ss dq21 nc v ss dq23 dq28 v ss dqs3 dq30 v ss v dd a14 a11 a6 a4 a0 ba1 cs0 odt0 v dd v ss dq37 dm4 dq38 v ss dq45 dqs5 v ss dq47 dq52 v ss ck1 dm6 dq54 v ss dq61 dqs7 v ss dq63 sa0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 001 pin 005 pin 009 pin 013 pin 017 pin 021 pin 025 pin 029 pin 033 pin 037 - - - - - - - - - - pin 003 pin 007 pin 011 pin 015 pin 019 pin 023 pin 027 pin 031 pin 035 pin 039 - - - - - - - - - - v ref dq0 v ss dqs0 dq2 v ss dq9 dqs1 v ss dq11 dq1 dqs0 v ss dq3 dq8 v ss dqs1 dq10 v ss pin 043 pin 047 pin 051 pin 055 pin 059 pin 063 pin 067 pin 071 pin 075 pin 079 pin 083 pin 087 pin 091 pin 095 pin 099 pin 103 pin 107 pin 111 pin 115 pin 119 pin 123 pin 127 pin 131 pin 135 pin 139 pin 143 pin 147 pin 151 pin 155 pin 159 pin 163 pin 167 pin 171 pin 175 pin 179 pin 183 pin 187 pin 191 pin 195 pin 199 dq16 v ss dqs2 dq18 v ss dq25 dm3 v ss dq27 cke0 nc v dd a9 v dd a3 v dd ba0 v dd nc/cs1 odt1 dq32 v ss dqs4 dq34 v ss dq41 dm5 dq42 v ss dq49 nc dqs6 v ss dq51 dq56 v ss v ss dq59 sda v dd spd - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 041 pin 045 pin 049 pin 053 pin 057 pin 061 pin 065 pin 069 pin 073 pin 077 pin 081 pin 085 pin 089 pin 093 pin 097 pin 101 pin 105 pin 109 pin 113 pin 117 pin 121 pin 125 pin 129 pin 133 pin 137 pin 141 pin 145 pin 149 pin 153 pin 157 pin 161 pin 165 pin 169 pin 173 pin 177 pin 181 pin 185 pin 189 pin 193 pin 197 v ss dq17 dqs2 v ss dq19 dq24 v ss nc dq26 v ss v dd nc a12 a8 a5 a1 a10/ap we cas v dd v ss dq33 dqs4 v ss dq35 dq40 v ss v ss dq43 dq48 v ss v ss dqs6 dq50 v ss dq57 dm7 dq58 v ss scl - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - v ss frontside backside dq4 v ss
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 14 rev. 0.91, 2004-06 09122003-ftxn-km26 table 8 input/output functional description symbol type polarity function ck[1:0], ck [1:0] i cross point the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and the falling edge of ck . a delay locked loop (dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. cke[1:0] i active high activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s [1:0] i active low enables the associated ddr2 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s0; rank 1 is selected by s1. ras , cas , we iactive low when sampled at the cross point of the rising edge of ck,and falling edge of ck , ras , cas and we define the operation to be executed by the sdram. ba[1:0] i ? selects internal sdram memory bank odt[1:0] i active high asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr2 sdram mode register. a[9:0], a10/ap, a[13:11] i ? during a bank activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of ck and falling edge of ck . during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba[1:0] to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba[1:0] inputs. if ap is low, then ba[1:0] are used to define which bank to precharge. dq[63:0] i/o ? data input/output pins dm[7:0] i active high the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect . dqs[7:0], dqs [7:0] i/o cross point the data strobes, associated with one data byte, sourced with data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode the data strobe is sourced by the ddr2 sdram and is sent at the leading edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs . if the module is to be operated in single ended strobe mode, all dqs signals must be tied on the system board to v ss through a 20 ohm to 10 kohm resistor and ddr2 sdram mode registers programmed appropriately. v dd , v ddspd , v ss supply ? power supplies for core, i/o, serial presence detect, and ground for the module. sda i/o ? this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resistor must be connected from sda to v ddspd on the motherboard to act as a pull-up. scl i ? this signal is used to clock data into and out of the spd eeprom. sa[1:0] i ? address pins used to select the serial presence detect base address.
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram block diagrams data sheet 15 rev. 0.91, 2004-06 09122003-ftxn-km26 2 block diagrams figure 2 block diagram raw card c (32m x 64, 1 rank, x16) note 1. dq, dqs, dqs, dm resistors are 22 ? 5% 2. s0 , s1 , ban, an, ras , cas , we, odt0, odt1, ckeo, cke1 resistors are 3 ? 5% ba0, ba1 ba0, ba1 : sdrams d0 - d3 a0 - a12 a0 - a12 : sdrams d0 - d3 ras ras : sdrams d0 - d3 cas cas : sdrams d0 - d3 we we : sdrams d0 - d3 dq-to-i/o wiring may be changed within a byte dq/dqs/dqs/dm/cke/cs relationships must be maintained as shown dq/dqs/dqs/dm resistors are 22 ? +/- 5% address and control resistors are 3.0 ? +/- 5% clock wiring clock input sdrams ck0, ck0 ck1, ck1 2 sdrams 2 sdrams v dd v ss d0 - d3 (vdd&vddq) vref v ddspd eeprom d0 - d3 d0 - d3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 o 12 d2 cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ldm ldqs ldqs udm udqs udqs i/o 8 i/o 9 i/ o 10 i/o 11 i/ i/o 13 i/0 14 i/o 15 dm5 dqs5 dqs5 dm4 dqs4 dqs4 o 12 d3 cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ldm ldqs ldqs udm udqs udqs i/o 8 i/o 9 i/ o 10 i/o 11 i/ i/ o 13 i/0 14 i/o 15 dm7 dqs7 dqs7 dm6 dqs6 dqs6 dq52 dq53 dq54 dq55 dq48 dq49 dq51 dq50 cke0 cke : sdrams d0 - d3 odt0 odt : sdrams d0 - d3 cs0 dm1 dqs1 dqs1 dm0 dqs0 dqs0 o 12 d1 cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ldm ldqs ldqs udm udqs udqs i/o 8 i/o 9 i/o 10 i/o 11 i/ i/ o 13 i/0 14 i/o 15 dm3 dqs3 dqs3 dm2 dqs2 dqs2 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 o 12 d0 cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ldm ldqs ldqs udm udqs udqs i/o 8 i/o 9 i/ o 10 i/o 11 i/ i/o 13 i/0 14 i/o 15 a0 serial pd a1 sa0 sa1 scl sda wp a2 3.0 ? +/- 5% 3.0 ? +/- 5%
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram block diagrams data sheet 16 rev. 0.91, 2004-06 09122003-ftxn-km26 figure 3 block diagram raw card a (64m x 64, 2 ranks, x16) note 1. dq, dqs, dqs, dm resistors are 22 ? 5% 2. s0 , s1 , ban, an, ras , cas , we, odt0, odt1, ckeo, cke1 resistors are 3 ? 5% cs0 ba0, ba1 ba0, ba1 : sdrams d0 - d3 a0 - a12 a0 - a12 : sdrams d0 - d3 ras ras : sdrams d0 - d3 cas cas : sdrams d0 - d3 we we : sdrams d0 - d3 clock wiring clock input sdrams ck0, ck0 ck1, ck1 4 sdrams 4 sdrams v dd v ss d0 - d7 (vdd & vddq) vref v ddspd eeprom d0 - d7 d0 - d7 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm1 dqs1 dqs1 dm0 dqs0 dqs0 o 12 d1 cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ldm ldqs ldqs udm udqs udqs i/o 8 i/o 9 i/ o 10 i/o 11 i/ i/ o 13 i/0 14 i/o 15 dm3 dqs3 dqs3 dm2 dqs2 dqs2 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 o 12 d2 cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ldm ldqs ldqs udm udqs udqs i/o 8 i/o 9 i/o 10 i/o 11 i/ i/o 13 i/0 14 i/o 15 dm5 dqs5 dqs5 dm4 dqs4 dqs4 o 12 d3 cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ldm ldqs ldqs udm udqs udqs i/o 8 i/o 9 i/ o 10 i/o 11 i/ i/o 13 i/0 14 i/o 15 dm7 dqs7 dqs7 dm6 dqs6 dqs6 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 dq52 dq53 dq54 dq55 dq48 dq49 dq51 dq50 o 12 d0 cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ldm ldqs ldqs udm udqs udqs i/o 8 i/o 9 i/o 10 i/o 11 i/ i/ o 13 i/0 14 i/o 15 o 12 d4 cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ldm ldqs ldqs udm udqs udqs i/o 8 i/o 9 i/ o 10 i/o 11 i/ i/o 13 i/0 14 i/o 15 o 12 d5 cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ldm ldqs ldqs udm udqs udqs i/o 8 i/o 9 i/o 10 i/o 11 i/ i/o 13 i/0 14 i/o 15 o 12 d6 cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ldm ldqs ldqs udm udqs udqs i/o 8 i/o 9 i/o 10 i/o 11 i/ i/o 13 i/0 14 i/o 15 o 12 d7 cs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ldm ldqs ldqs udm udqs udqs i/o 8 i/o 9 i/o 10 i/o 11 i/ i/o 13 i/0 14 i/o 15 cs1 odt0 odt : sdrams d0 - d3 odt1 odt : sdrams d4 - d7 cke1 cke : sdrams d4 - d7 cke0 cke : sdrams d0 - d3 a0 serial pd a1 sa0 sa1 scl sda wp a2 3.0 ? +/- 5% dq-to-i/o wiring may be changed within a byte dq/dqs/dqs/dm/cke/cs relationships must be maintained as shown dq/dqs/dqs/dm resistors are 22 ? +/- 5% address and control resistors are 3.0 ? +/- 5%
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram block diagrams data sheet 17 rev. 0.91, 2004-06 09122003-ftxn-km26 figure 4 block diagram raw card d (128m x 64, 2 ranks, x8) note 1. dq, dqs, dqs, dm resistors are 22 ? 5% 2. s0 , s1 , ban, an, ras , cas , we, odt0, odt1, ckeo, cke1 resistors are 3 ? 5% d1, d9 (dual die) d2, d10 (dual die) cs0 odt0 cke0 cs1 odt1 cke1 10 ? +/- 5% dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dq50 dq52 dq53 dq54 dq55 dq48 dq49 dq51 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm0 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 d0, d8 (dual die) dqs0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs0 dm cs0 odt0 cke0 cs1 odt1 cke1 dqs dqs dm1 dqs1 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs1 dm cs0 odt0 cke0 cs1 odt1 cke1 dqs dqs dm2 dqs2 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs2 dm cs0 odt0 cke0 cs1 odt1 cke1 dqs dqs d3, d11 (dual die) dqs3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs3 dm cs0 odt0 cke0 cs1 odt1 cke1 dqs dqs dm3 dm4 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 d4, d12 (dual die) dqs4 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs4 dm cs0 odt0 cke0 cs1 odt1 cke1 dqs dqs dm5 d5, d13 (dual die) dqs5 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs5 dm cs0 odt0 cke0 cs1 odt1 cke1 dqs dqs dm6 d6, d14 (dual die) dqs6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs6 dm cs0 odt0 cke0 cs1 odt1 cke1 dqs dqs d7, d15 (dual die) dqs7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs7 dm cs0 odt0 cke0 cs1 odt1 cke1 dqs dqs dm7 a0 serial pd a1 a2 sa0 sa1 scl sda wp d0 - d15, vdd, vddq eeprom d0 - d15 d0 - d15 vdd v ss vref v ddspd ba0, ba1 ba0, ba1 : sdrams d0 - d15 a0 - a13 a0 - a13 : sdrams d0 - d15 ras ras : sdrams d0 - d15 cas cas : sdrams d0 - d15 we we : sdrams d0 - d15 10 ? +/- 5% unless otherwise noted, resistor values are 22 ? +/- 5%. dq wiring may differ from that described in this drawing, however dq, dm, dqs, dqs relationship are maintained as shown clock wiring clock input sdrams ck0, ck0 ck1, ck1 8 loads 8 loads d2, d10 (dual die) d1, d0 (dual die)
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram electrical characteristics data sheet 18 rev. 0.91, 2004-06 09122003-ftxn-km26 3 electrical characteristics table 9 absolute maximum ratings parameter symbol limit values unit note/test condition min. max. voltage on any pins relative to v ss v in , v out ? 0.5 2.3 v 1) 1) stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on v dd relative to v ss v dd ? 1.0 2.3 v 1) voltage on v dd q relative to v ss v ddq ? 0.5 2.3 1) barometric pressure (operating & storage) +69 +105 kpa 1) storage humidity (without condensation) h stg 595% 1) table 10 operating temperature range parameter symbol limit values unit notes min. max. dimm module operating temperature range (ambient) t opr 0+65c dram component case temperature range t case 0+95c 1)2)3)4) 1) dram component case temperature is the surface temperature in the center on the top side of any of the drams. for measurement conditions, please refer to the jedec document jesd51-2 2) within the dram component case temperature range all dram specifications will be supported 3) above 85 c dram case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s. 4) self-refresh period is hard-coded in the drams and therefore it is imperative that the system ensures the dram is below 85 c case temperature before initiating self-refresh operation. storage temperature t stg ? 55 +100 c barometric pressure (operating & storage) +69 +105 kpa 5) 5) up to 3000 m. operating humidity (relative) h opr 10 90 % table 11 supply voltage levels and dc operating conditions parameter symbol limit values unit notes min. nom. max. device supply voltage v dd 1.7 1.8 1.9 v output supply voltage v ddq 1.7 1.8 1.9 v 1) 1) under all conditions, v ddq must be less than or equal to v dd input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2) 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc). v ref is also expected to track noise variations in v ddq . spd supply voltage v ddspd 1.7 ? 3.6 v dc input logic high v ih (dc) v ref +0.125 ? v ddq +0.3 v dc input logic low v il (dc) ? 0.30 ? v ref ?0.125 v in / output leakage current i l ? 5 ? 5 a 3) 3) for any pin on the dimm connector under test input of 0 v v in v ddq +0.3v.
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram i dd specifications and conditions data sheet 19 rev. 0.91, 2004-06 09122003-ftxn-km26 4 i dd specifications and conditions table 12 i dd measurement conditions 1)2) parameter symbol operating current 0 one bank active - precharge; t ck = t ckmin. , t rc = t rcmin ., t ras = t rasmin. , cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching . i dd0 operating current 1 one bank active - read - precharge; i out = 0 ma, bl = 4, t ck = t ckmin. , t rc = t rcmin ., t ras = t rasmin. , t rcd = t rcdmin. ,al = 0, cl = cl min .; cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 precharge power-down current other control and address inputs are stable, data bus inputs are floating . i dd2p precharge standby current all banks idle; cs is high; cke is high; t ck = t ckmin. ; other control and address inputs are switching, data bus inputs are switching. i dd2n precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ckmin. ; other control and address inputs are stable, data bus inputs are floating. i dd2q active power-down current all banks open; t ck = t ckmin. , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to ?0? (fast power-down exit); i dd3p(0) active power-down current all banks open; tck = t ckmin. , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to ?1? (slow power-down exit); i dd3p(1) active standby current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min. ; t ck = t ckmin .; t ras = t rasmax. , t rp = t rpmin. ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd3n operating current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min. ; t ck = t ckmin. ; t ras = t rasmax. , t rp = t rpmin. ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl min. ; t ck = t ckmin. ; t ras = t rasmax. , t rp = t rpmin. ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w burst refresh current t ck = t ckmin ., refresh command every t rfc = t rfcmin. interval, cke is high, cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5b distributed refresh current t ck = t ckmin. , refresh command every t rfc = t refi interval, cke is low and cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5d
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram i dd specifications and conditions data sheet 20 rev. 0.91, 2004-06 09122003-ftxn-km26 self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. reset = low. i dd6 current values are guaranteed up to t case of 85 c max. i dd6 all bank interleave read current all banks are being interleaved at minimum t rc without violating t rrd using a burst length of 4. control and address bus inputs are stable during deselects. i out = 0 ma. i dd7 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) for details and notes see the relevant infineon component data sheet table 13 i dd specification hys64t[32000/64020][g/h]dl product type hys64t32000gdl-5-a hys64t32000hdl-5-a hys64t64020gdl-5-a hys64t64020hdl-5-a hys64t32000gdl-3.7-a hys64t32000hdl-3.7-a hys64t64020gdl-3.7-a hys64t64020hdl-3.7-a unit notes organization 256 mb 256 mb 512 mb 512 mb 256 mb 256 mb 512 mb 512 mb 64 64 64 64 64 64 64 64 1 rank 1 rank 2 ranks 2 ranks 1 rank 1 rank 2 ranks 2 ranks symbol max. max. max. max. max. max. max. max. i dd0 280 280 300 300 320 320 340 340 ma 1)2) 1) calculated values from component data. odt disabled. i dd1 , i dd4r and i dd7 are defined with the outputs disabled 2) the other rank is in idd2p precharge power-down standby current mode i dd1 300 300 320 320 360 360 380 380 ma 1)2) i dd2p 20 20 30 30 20 20 30 30 ma 1)3) 3) both ranks are in the same idd current mode i dd2n 130 130 260 260 160 160 320 320 ma 1)3) i dd2q 100 100 200 200 120 120 240 240 ma 1)3) i dd3p( mrs = 0) 50 50 100 100 60 60 130 130 ma 1)3) i dd3p( mrs = 1) 20 20 40 40 20 20 40 40 ma 1)3) i dd3n 140 140 280 280 160 160 320 320 ma 1)3) i dd4r 340 340 360 360 400 400 420 420 ma 1)2) i dd4w 360 360 380 380 440 440 460 460 ma 1)2) i dd5b 480 480 500 500 520 520 540 540 ma 1)2) i dd5d 20 20 50 50 20 20 50 50 ma 1)3) i dd6 20 20 30 30 20 20 30 30 ma 1)4) 4) standard i dd7 840 840 860 860 880 880 900 900 ma 1)2) table 12 i dd measurement conditions 1)2) (cont?d) parameter symbol
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram i dd specifications and conditions data sheet 21 rev. 0.91, 2004-06 09122003-ftxn-km26 table 14 i dd specification hys64t128021[g/h]dl product type hys64t128021gdl-5-a HYS64T128021HDL-5-A hys64t128021gdl-3.7-a hys64t128021hdl-3.7-a unit notes organization 1 gb 1 gb 1 gb 1 gb 64 64 64 64 2 ranks 2 ranks 2 ranks 2 ranks symbol max. max. max. max. i dd0 472 472 552 552 ma 1)2) 1) calculated values from component data. odt disabled. i dd1 , i dd4r and i dd7 are defined with the outputs disabled 2) the other rank is in idd2p precharge power-down standby current mode i dd1 512 512 632 632 ma 1)2) i dd2p 64 64 64 64 ma 1)3) 3) both ranks are in the same idd current mode i dd2n 512 512 640 640 ma 1)3) i dd2q 400 400 480 480 ma 1)3) i dd3p( mrs = 0) 208 208 256 256 ma 1)3) i dd3p( mrs = 1) 80 80 80 80 ma 1)3) i dd3n 560 560 640 640 ma 1)3) i dd4r 592 592 752 752 ma 1)2) i dd4w 632 632 792 792 ma 1)2) i dd5b 976 976 1060 1060 ma 1)2) i dd5d 96 96 96 96 ma 1)3) i dd6 64 64 64 64 ma 1)4) 4) standard i dd7 1072 1072 1312 1312 ma 1)2)
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram i dd specifications and conditions data sheet 22 rev. 0.91, 2004-06 09122003-ftxn-km26 4.1 i dd test conditions for testing the idd parameters, the timing parameters as in table 15 are used. 4.2 odt (on die termination) current the odt function adds additional current consumption to the ddr2 sdram when enabled by the emrs(1). depending on address bits a[6,2] in the emrs(1) a ?weak? or ?strong? termination can be selected. the current consumption for any terminated input pin, depends on the input pin is in tri-state or driving ?0? or ?1?, as long a odt is enabled during a given period of time. note: for power consumption calculations the odt duty cycle has to be taken into account table 15 i dd measurement test condition parameter symbol -3.7 -5 unit pc2-4200-4-4-4 pc2-3200-3-3-3 cas latency cl min 43 t ck clock cycle time t ckmin 3.75 5 ns active to read or write delay t rcdmin 15 15 ns active to active / auto-refresh command period t rcmin 60 55 ns active bank a to active bank b command delay t rrdmin 10 10 ns active to precharge command t rasmin 45 40 ns t rasmax 70000 70000 ns precharge command period t rpmin 15 15 ns auto-refresh to active / auto-refresh command period t rfcmin 105 105 ns average periodic refresh interval t refi 7.8 7.8 s table 16 odt current per terminated pin parameter symbol min. typ. max. unit emrs(1) state enabled odt current per dq odt is high; data bus inputs are floating i odto 5 6 7.5 ma/dq a6 = 0, a2 = 1 2.5 3 3.75 ma/dq a6 = 1, a2 = 0 active odt current per dq odt is high; worst case of data bus inputs are stable or switching. i odtt 10 12 15 ma/dq a6 = 0, a2 = 1 5 6 7.5 ma/dq a6 = 1, a2 = 0
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram electrical characteristics & ac timings data sheet 23 rev. 0.91, 2004-06 09122003-ftxn-km26 5 electrical characteristics & ac timings table 17 ac timing - absolute specificatioins ?5/?3.7 parameter symbol ?3.7 ?5 unit notes pc2-4200s pc2-3200s min. max. min. max. dq output access time from ck/ck t ac -500 +500 ? 600 + 600 ps 1) dqs output access time from ck/ck t dqsck ? 450 + 450 ? 500 + 500 ps 1) ck, ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 1) ck, ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 1) clock half period t hp min. ( t cl, t ch )min. ( t cl, t ch ) t ck 1) clock cycle time t ck 5000 8000 5000 8000 ps 1)2) 3750 8000 5000 8000 ps 1)3) address and control input setup time t is 600 ? 600 ? ps 1) address and control input hold time t ih 600 ? 600 ? ps 1) dq and dm input hold time t dh 350 ? 400 ? ps 1) dq and dm input setup time t ds 350 ? 400 ? ps 1) control and addr. input pulse width (each input) t ipw 0.6 ? 0.6 ? t ck 1) dq and dm input pulse width (each input) t dipw 0.35 ? 0.35 ? t ck 1) data-out high-impedance time from ck/ck t hz ? t acmax ? t acmax ps 1) dq low-impedance from ck / ck t lz(dq) 2 t acmin t acmax 2 t acmin t acmax ps 1) dqs low-impedance from ck / ck t lz(dqs) t acmin t acmax t acmin t acmax ps 1) dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ? 350 ps 1) data hold skew factor t qhs ? 400 ? 450 ps 1) data output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ? t ck 1) write command to 1st dqs latching transition t dqss wl - 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 t ck 1) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 1) dqs falling edge to clk setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 1) dqs falling edge hold time from clk (write cycle) t dsh 0.2 ? 0.2 ? t ck 1) mode register set command cycle time t mrd 2?2? t ck 1) write preamble t wpre 0.25 ? 0.25 ? t ck 1) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 1) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 1) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 1) active to precharge command t ras 45 70000 40 70000 ns 1)
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram electrical characteristics & ac timings data sheet 24 rev. 0.91, 2004-06 09122003-ftxn-km26 active to active/auto-refresh command period t rc 60 ? 55 ? ns 1) auto-refresh to active/auto-refresh command period t rfc 105 ? 105 ? ns 1) active to read or write delay (with and without auto-precharge) delay t rcd 15 ? 15 ? ns 1) precharge command period t rp 15 ? 15 ? ns 1) active bank a to active bank b command t rrd 10 ? 10 ? ns 1) cas a to cas b command period t ccd 2?2? t ck 1) write recovery time t wr 15 ? 15 ? ns 1) auto precharge write recovery + precharge time t dal wr + t rp ?wr+ t rp ? t ck 1) internal write to read command delay t wtr 7.5 ? 10 ? ns 1) internal read to precharge command delay t rtp 7.5 ? 7.5 ? ns 1) exit power down to any valid command (other than nop or deselect) t xard 2?2? t ck 1) exit active power-down mode to read command (slew exit, lower power) t xards 6 ? al ? 6 ? al ? t ck 1) exit precharge power-down to any valid command (other than nop or deselect) t xp 2?2? t ck 1) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 1) exit self-refresh to non-read command t xsnr t rfc + 10 ? t rfc + 10 ? ns 1) cke minimum high and low pulse width t cke 3?3? t ck 1) ocd drive mode output delay t oit 0 12 0 12 ns 1) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ? t is + t ck + t ih ?ns 1) average periodic refresh interval t refi ? 7.8 ? 7.8 s 1)4) ? 3.9 ? 3.9 1)5) 1) for details and notes see the relevant infineon component datasheet 2) cl = 3 3) cl = 4 & 5 4) 0c t case 85 c 5) 85 c < t case 95 c table 17 ac timing - absolute specificatioins ?5/?3.7 parameter symbol ?3.7 ?5 unit notes pc2-4200s pc2-3200s min. max. min. max.
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram electrical characteristics & ac timings data sheet 25 rev. 0.91, 2004-06 09122003-ftxn-km26 table 18 odt ac electrical characteristics and operating conditions (all speed bins) symbol parameter / condition min. max. unit t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac(min) t ac(max) + 1 ns ns t aonpd odt turn-on (power-down modes) t ac(min) + 2 ns 2 t ck + t ac(max) + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac(min) t ac(max) + 0.6 ns ns t aofpd odt turn-off delay (power-down modes) t ac(min) + 2 ns 2.5 t ck + t ac(max) + 1 ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 26 rev. 0.91, 2004-06 09122003-ftxn-km26 6 spd codes table 19 spd codes for hys 64t[32000/64020] pc2?4200s product type hys64t64020gdl?3.7?a hys64t64020hdl?3.7?a hys64t32000gdl?3.7?a hys64t32000hdl?3.7?a organization 512 mb 512 mb 256 mb 256 mb 64 64 64 64 2 ranks ( 16) 2 ranks ( 16) 1 rank ( 16) 1 rank ( 16) label code pc2?4200s?444 pc2?4200s?444 pc2?4200s?444 pc2?4200s?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0a 0a 0a 0a 5 dimm rank and stacking information 61 61 60 60 6 data width40404040 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 3d 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 50 11 error correction support (non-ecc, ecc) 00 00 00 00 12 refresh rate and type 82 82 82 82 13 primary sdram width 10 10 10 10 14 error checking sdram width 00 00 00 00
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 27 rev. 0.91, 2004-06 09122003-ftxn-km26 15 not used 00 00 00 00 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 38 38 38 38 19 not used 00 00 00 00 20 dimm type information 04 04 04 04 21 dimm attributes 00 00 00 00 22 component attributes 01 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 3d 24 t ac sdram @ cl max - 1 [ns] 50 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 26 t ac sdram @ cl max - 2 [ns] 60 60 60 60 27 t rp.min [ns] 3c 3c 3c 3c 28 t rrd.min [ns] 28 28 28 28 29 t rcd.min [ns] 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 40 40 40 40 32 t as.min and t cs.min [ns] 25 25 25 25 33 t ah.min and t ch.min [ns] 37 37 37 37 34 t ds.min [ns] 10 10 10 10 35 t dh.min [ns] 22 22 22 22 table 19 spd codes for hys 64t[32000/64020] pc2?4200s product type hys64t64020gdl?3.7?a hys64t64020hdl?3.7?a hys64t32000gdl?3.7?a hys64t32000hdl?3.7?a organization 512 mb 512 mb 256 mb 256 mb 64 64 64 64 2 ranks ( 16) 2 ranks ( 16) 1 rank ( 16) 1 rank ( 16) label code pc2?4200s?444 pc2?4200s?444 pc2?4200s?444 pc2?4200s?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 28 rev. 0.91, 2004-06 09122003-ftxn-km26 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension00000000 41 t rc.min [ns] 3c 3c 3c 3c 42 t rfc.min [ns] 69 69 69 69 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 1e 1e 1e 1e 45 t qhs.max [ns] 28 28 28 28 46 pll relock time 00 00 00 00 47 t case.max delta / ? t 4r4w delta 53 53 53 53 48 psi(t-a) dram 72 72 72 72 49 ? t 0 (dt0)52525252 50 ? t 2n (dt2n, udimm) or ? t 2q ( (dt2q, rdimm) 2b 2b 2b 2b 51 ? t 2p (dt2p) 1d 1d 1d 1d 52 ? t 3n (dt3n) 1d 1d 1d 1d 53 ? t 3p.fast (dt3p fast)23232323 54 ? t 3p.slow (dt3p slow)16161616 55 ? t 4r (dt4r) / ? t 4r4w s sign (dt4r4w) 36 36 36 36 56 ? t 5b (dt5b) 1c 1c 1c 1c 57 ? t 7 (dt7)30303030 58 psi(ca) pll 00 00 00 00 59 psi(ca) reg00000000 table 19 spd codes for hys 64t[32000/64020] pc2?4200s product type hys64t64020gdl?3.7?a hys64t64020hdl?3.7?a hys64t32000gdl?3.7?a hys64t32000hdl?3.7?a organization 512 mb 512 mb 256 mb 256 mb 64 64 64 64 2 ranks ( 16) 2 ranks ( 16) 1 rank ( 16) 1 rank ( 16) label code pc2?4200s?444 pc2?4200s?444 pc2?4200s?444 pc2?4200s?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 29 rev. 0.91, 2004-06 09122003-ftxn-km26 60 ? t pll (dtpll)00000000 61 ? t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 11 11 11 11 63 checksum of bytes 0- 62 bc bc bb bb 64 jedec id code of infineon (1) c1 c1 c1 c1 65 jedec id code of infineon (2) 00 00 00 00 66 jedec id code of infineon (3) 00 00 00 00 67 jedec id code of infineon (4) 00 00 00 00 68 jedec id code of infineon (5) 00 00 00 00 69 jedec id code of infineon (6) 00 00 00 00 70 jedec id code of infineon (7) 00 00 00 00 71 jedec id code of infineon (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 36 36 74 product type, char 2 34 34 34 34 75 product type, char 3 54 54 54 54 76 product type, char 4 36 36 33 33 77 product type, char 5 34 34 32 32 78 product type, char 6 30 30 30 30 table 19 spd codes for hys 64t[32000/64020] pc2?4200s product type hys64t64020gdl?3.7?a hys64t64020hdl?3.7?a hys64t32000gdl?3.7?a hys64t32000hdl?3.7?a organization 512 mb 512 mb 256 mb 256 mb 64 64 64 64 2 ranks ( 16) 2 ranks ( 16) 1 rank ( 16) 1 rank ( 16) label code pc2?4200s?444 pc2?4200s?444 pc2?4200s?444 pc2?4200s?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 30 rev. 0.91, 2004-06 09122003-ftxn-km26 79 product type, char 7 32 32 30 30 80 product type, char 8 30 30 30 30 81 product type, char 9 47 48 47 48 82 product type, char 10 44 44 44 44 83 product type, char 11 4c 4c 4c 4c 84 product type, char 12 33 33 33 33 85 product type, char 13 2e 2e 2e 2e 86 product type, char 14 37 37 37 37 87 product type, char 15 41 41 41 41 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 1x 1x 1x 1x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 module manufacturing date week xx xx xx xx table 19 spd codes for hys 64t[32000/64020] pc2?4200s product type hys64t64020gdl?3.7?a hys64t64020hdl?3.7?a hys64t32000gdl?3.7?a hys64t32000hdl?3.7?a organization 512 mb 512 mb 256 mb 256 mb 64 64 64 64 2 ranks ( 16) 2 ranks ( 16) 1 rank ( 16) 1 rank ( 16) label code pc2?4200s?444 pc2?4200s?444 pc2?4200s?444 pc2?4200s?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 31 rev. 0.91, 2004-06 09122003-ftxn-km26 96 module serial number (1) xx xx xx xx 97 module serial number (2) xx xx xx xx 98 module serial number (3) xx xx xx xx 99 module serial number (4) xx xx xx xx 100 - 127 not used 00 00 00 00 128- 255 blank ff ff ff ff table 19 spd codes for hys 64t[32000/64020] pc2?4200s product type hys64t64020gdl?3.7?a hys64t64020hdl?3.7?a hys64t32000gdl?3.7?a hys64t32000hdl?3.7?a organization 512 mb 512 mb 256 mb 256 mb 64 64 64 64 2 ranks ( 16) 2 ranks ( 16) 1 rank ( 16) 1 rank ( 16) label code pc2?4200s?444 pc2?4200s?444 pc2?4200s?444 pc2?4200s?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 32 rev. 0.91, 2004-06 09122003-ftxn-km26 table 20 spd codes for hys 64t[32000/64020] pc2-3200s product type hys64t64020gdl?5?a hys64t64020hdl?5?a hys64t32000gdl?5?a hys64t32000hdl?5?a organization 512 mb 512 mb 256 mb 256 mb 64 64 64 64 2 ranks ( 16) 2 ranks ( 16) 1 rank ( 16) 1 rank ( 16) label code pc2?3200s?333 pc2?3200s?333 pc2?3200s?333 pc2?3200s?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0a 0a 0a 0a 5 dimm rank and stacking information 61 61 60 60 6 data width40404040 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 50 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 60 60 60 60 11 error correction support (non-ecc, ecc) 00 00 00 00 12 refresh rate and type 82 82 82 82 13 primary sdram width 10 10 10 10 14 error checking sdram width 00 00 00 00 15 not used 00 00 00 00
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 33 rev. 0.91, 2004-06 09122003-ftxn-km26 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 38 38 38 38 19 not used 00 00 00 00 20 dimm type information 04 04 04 04 21 dimm attributes 00 00 00 00 22 component attributes 01 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 50 50 50 50 24 t ac sdram @ cl max - 1 [ns] 60 60 60 60 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 26 t ac sdram @ cl max - 2 [ns] 60 60 60 60 27 t rp.min [ns] 3c 3c 3c 3c 28 t rrd.min [ns] 28 28 28 28 29 t rcd.min [ns] 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 40 40 40 40 32 t as.min and t cs.min [ns] 35 35 35 35 33 t ah.min and t ch.min [ns] 47 47 47 47 34 t ds.min [ns] 15 15 15 15 35 t dh.min [ns] 27 27 27 27 36 t wr.min [ns] 3c 3c 3c 3c table 20 spd codes for hys 64t[32000/64020] pc2-3200s product type hys64t64020gdl?5?a hys64t64020hdl?5?a hys64t32000gdl?5?a hys64t32000hdl?5?a organization 512 mb 512 mb 256 mb 256 mb 64 64 64 64 2 ranks ( 16) 2 ranks ( 16) 1 rank ( 16) 1 rank ( 16) label code pc2?3200s?333 pc2?3200s?333 pc2?3200s?333 pc2?3200s?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 34 rev. 0.91, 2004-06 09122003-ftxn-km26 37 t wtr.min [ns] 28 28 28 28 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension00000000 41 t rc.min [ns] 3c 3c 3c 3c 42 t rfc.min [ns] 69 69 69 69 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 23 23 23 23 45 t qhs.max [ns] 2d 2d 2d 2d 46 pll relock time 00 00 00 00 47 t case.max delta / ? t 4r4w delta 51 51 51 51 48 psi(t-a) dram 72 72 72 72 49 ? t 0 (dt0)42424242 50 ? t 2n (dt2n, udimm) or ? t 2q ( (dt2q, rdimm) 23 23 23 23 51 ? t 2p (dt2p) 1d 1d 1d 1d 52 ? t 3n (dt3n) 19 19 19 19 53 ? t 3p.fast (dt3p fast)1c1c1c1c 54 ? t 3p.slow (dt3p slow)16161616 55 ? t 4r (dt4r) / ? t 4r4w s sign (dt4r4w) 2e 2e 2e 2e 56 ? t 5b (dt5b) 1a 1a 1a 1a 57 ? t 7 (dt7)2d2d2d2d 58 psi(ca) pll 00 00 00 00 59 psi(ca) reg00000000 60 ? t pll (dtpll)00000000 table 20 spd codes for hys 64t[32000/64020] pc2-3200s product type hys64t64020gdl?5?a hys64t64020hdl?5?a hys64t32000gdl?5?a hys64t32000hdl?5?a organization 512 mb 512 mb 256 mb 256 mb 64 64 64 64 2 ranks ( 16) 2 ranks ( 16) 1 rank ( 16) 1 rank ( 16) label code pc2?3200s?333 pc2?3200s?333 pc2?3200s?333 pc2?3200s?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 35 rev. 0.91, 2004-06 09122003-ftxn-km26 61 ? t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 11 11 11 11 63 checksum of bytes 0- 62 0e 0e 0d 0d 64 jedec id code of infineon (1) c1 c1 c1 c1 65 jedec id code of infineon (2) 00 00 00 00 66 jedec id code of infineon (3) 00 00 00 00 67 jedec id code of infineon (4) 00 00 00 00 68 jedec id code of infineon (5) 00 00 00 00 69 jedec id code of infineon (6) 00 00 00 00 70 jedec id code of infineon (7) 00 00 00 00 71 jedec id code of infineon (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 36 36 74 product type, char 2 34 34 34 34 75 product type, char 3 54 54 54 54 76 product type, char 4 36 36 33 33 77 product type, char 5 34 34 32 32 78 product type, char 6 30 30 30 30 79 product type, char 7 32 32 30 30 80 product type, char 8 30 30 30 30 table 20 spd codes for hys 64t[32000/64020] pc2-3200s product type hys64t64020gdl?5?a hys64t64020hdl?5?a hys64t32000gdl?5?a hys64t32000hdl?5?a organization 512 mb 512 mb 256 mb 256 mb 64 64 64 64 2 ranks ( 16) 2 ranks ( 16) 1 rank ( 16) 1 rank ( 16) label code pc2?3200s?333 pc2?3200s?333 pc2?3200s?333 pc2?3200s?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 36 rev. 0.91, 2004-06 09122003-ftxn-km26 81 product type, char 9 47 48 47 48 82 product type, char 10 44 44 44 44 83 product type, char 11 4c 4c 4c 4c 84 product type, char 12 35 35 35 35 85 product type, char 13 41 41 41 41 86 product type, char 14 20 20 20 20 87 product type, char 15 20 20 20 20 88 product type, char 16 20 20 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 1x 1x 1x 1x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 module manufacturing date week xx xx xx xx 96 module serial number (1) xx xx xx xx table 20 spd codes for hys 64t[32000/64020] pc2-3200s product type hys64t64020gdl?5?a hys64t64020hdl?5?a hys64t32000gdl?5?a hys64t32000hdl?5?a organization 512 mb 512 mb 256 mb 256 mb 64 64 64 64 2 ranks ( 16) 2 ranks ( 16) 1 rank ( 16) 1 rank ( 16) label code pc2?3200s?333 pc2?3200s?333 pc2?3200s?333 pc2?3200s?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 37 rev. 0.91, 2004-06 09122003-ftxn-km26 97 module serial number (2) xx xx xx xx 98 module serial number (3) xx xx xx xx 99 module serial number (4) xx xx xx xx 100 - 127 not used 00 00 00 00 128- 255 blank ff ff ff ff table 20 spd codes for hys 64t[32000/64020] pc2-3200s product type hys64t64020gdl?5?a hys64t64020hdl?5?a hys64t32000gdl?5?a hys64t32000hdl?5?a organization 512 mb 512 mb 256 mb 256 mb 64 64 64 64 2 ranks ( 16) 2 ranks ( 16) 1 rank ( 16) 1 rank ( 16) label code pc2?3200s?333 pc2?3200s?333 pc2?3200s?333 pc2?3200s?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 38 rev. 0.91, 2004-06 09122003-ftxn-km26 table 21 spd codes for hys64t128021[g/h]dl product type hys64t128021hdl?3.7?a hys64t128021gdl?3.7?a hys64t128021hdl?5?a hys64t128021gdl?5?a organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200s?444 pc2?4200s?444 pc2?3200s?444 pc2?3200s?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex 0 programmed spd bytes in eeprom 80 80 80 80 1 total number of bytes in eeprom 08 08 08 08 2 memory type (ddr2) 08 08 08 08 3 number of row addresses 0e 0e 0e 0e 4 number of column addresses 0a 0a 0a 0a 5 dimm rank and stacking information 61 61 61 61 6 data width 40 40 40 40 7 not used 00 00 00 00 8 interface voltage level 05 05 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 50 50 10 t ac sdram @ cl max (byte 18) [ns] 50 50 60 60 11 error correction support (non-ecc, ecc) 00 00 00 00 12 refresh rate and type 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 00 00 00 15 not used 00 00 00 00
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 39 rev. 0.91, 2004-06 09122003-ftxn-km26 16 burst length supported 0c 0c 0c 0c 17 number of banks on sdram device 04 04 04 04 18 supported cas latencies 38 38 38 38 19 not used 00 00 00 00 20 dimm type information 04 04 04 04 21 dimm attributes 00 00 00 00 22 component attributes 01 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 50 50 24 t ac sdram @ cl max - 1 [ns] 50 50 60 60 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 50 26 t ac sdram @ cl max - 2 [ns] 60 60 60 60 27 t rp.min [ns] 3c 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 2d 31 module density per rank 80 80 80 80 32 t as.min and t cs.min [ns] 25 25 35 35 33 t ah.min and t ch.min [ns] 37 37 47 47 34 t ds.min [ns] 10 10 15 15 35 t dh.min [ns] 22 22 27 27 table 21 spd codes for hys64t128021[g/h]dl product type hys64t128021hdl?3.7?a hys64t128021gdl?3.7?a hys64t128021hdl?5?a hys64t128021gdl?5?a organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200s?444 pc2?4200s?444 pc2?3200s?444 pc2?3200s?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 40 rev. 0.91, 2004-06 09122003-ftxn-km26 36 t wr.min [ns] 3c 3c 3c 3c 37 t wtr.min [ns] 1e 1e 28 28 38 t rtp.min [ns] 1e 1e 1e 1e 39 analysis characteristics 00 00 00 00 40 t rc and t rfc extension 00 00 00 00 41 t rc.min [ns] 3c 3c 3c 3c 42 t rfc.min [ns] 69 69 69 69 43 t ck.max [ns] 80 80 80 80 44 t dqsq.max [ns] 1e 1e 23 23 45 t qhs.max [ns] 28 28 2d 2d 46 pll relock time 00 00 00 00 47 t case.max delta / ? t 4r4w delta 51 51 51 51 48 psi(t-a) dram 78 78 78 78 49 ? t 0 (dt0) 3e 3e 32 32 50 ? t 2n (dt2n, udimm) or ? t 2q ( (dt2q, rdimm) 2e 2e 24 24 51 ? t 2p (dt2p) 1e 1e 1e 1e 52 ? t 3n (dt3n) 1e 1e 1b 1b 53 ? t 3p.fast (dt3p fast) 24 24 1e 1e 54 ? t 3p.slow (dt3p slow) 17 17 17 17 55 ? t 4r (dt4r) / ? t 4r4w s sign (dt4r4w) 34 34 28 28 56 ? t 5b (dt5b) 1e 1e 1b 1b 57 ? t 7 (dt7) 20 20 1e 1e 58 psi(ca) pll 00 00 00 00 59 psi(ca) reg 00 00 00 00 table 21 spd codes for hys64t128021[g/h]dl product type hys64t128021hdl?3.7?a hys64t128021gdl?3.7?a hys64t128021hdl?5?a hys64t128021gdl?5?a organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200s?444 pc2?4200s?444 pc2?3200s?444 pc2?3200s?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 41 rev. 0.91, 2004-06 09122003-ftxn-km26 60 ? t pll (dtpll) 00 00 00 00 61 ? t reg (dtreg) / toggle rate 00 00 00 00 62 spd revision 11 11 11 11 63 checksum of bytes 0- 62 d2 d2 26 26 64 jedec id code of infineon (1) c1 c1 c1 c1 65 jedec id code of infineon (2) 00 00 00 00 66 jedec id code of infineon (3) 00 00 00 00 67 jedec id code of infineon (4) 00 00 00 00 68 jedec id code of infineon (5) 00 00 00 00 69 jedec id code of infineon (6) 00 00 00 00 70 jedec id code of infineon (7) 00 00 00 00 71 jedec id code of infineon (8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 product type, char 1 36 36 36 36 74 product type, char 2 34 34 34 34 75 product type, char 3 54 54 54 54 76 product type, char 4 31 31 31 31 77 product type, char 5 32 32 32 32 78 product type, char 6 38 38 38 38 table 21 spd codes for hys64t128021[g/h]dl product type hys64t128021hdl?3.7?a hys64t128021gdl?3.7?a hys64t128021hdl?5?a hys64t128021gdl?5?a organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200s?444 pc2?4200s?444 pc2?3200s?444 pc2?3200s?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 42 rev. 0.91, 2004-06 09122003-ftxn-km26 79 product type, char 7 30 30 30 30 80 product type, char 8 32 32 32 32 81 product type, char 9 31 31 31 31 82 product type, char 10 48 47 48 47 83 product type, char 11 44 44 44 44 84 product type, char 12 4c 4c 4c 4c 85 product type, char 13 33 33 35 35 86 product type, char 14 2e 2e 41 41 87 product type, char 15 37 37 20 20 88 product type, char 16 41 41 20 20 89 product type, char 17 20 20 20 20 90 product type, char 18 20 20 20 20 91 module revision code 0x 0x 0x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 module manufacturing date week xx xx xx xx 96 module serial number (1) xx xx xx xx 97 module serial number (2) xx xx xx xx 98 module serial number (3) xx xx xx xx table 21 spd codes for hys64t128021[g/h]dl product type hys64t128021hdl?3.7?a hys64t128021gdl?3.7?a hys64t128021hdl?5?a hys64t128021gdl?5?a organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200s?444 pc2?4200s?444 pc2?3200s?444 pc2?3200s?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 43 rev. 0.91, 2004-06 09122003-ftxn-km26 99 module serial number (4) xx xx xx xx 100 - 127 not used 00 00 00 00 128- 255 blank ff ff ff ff table 21 spd codes for hys64t128021[g/h]dl product type hys64t128021hdl?3.7?a hys64t128021gdl?3.7?a hys64t128021hdl?5?a hys64t128021gdl?5?a organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200s?444 pc2?4200s?444 pc2?3200s?444 pc2?3200s?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex hex
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram package outlines data sheet 44 rev. 0.91, 2004-06 09122003-ftxn-km26 7 package outlines figure 5 package outline l-dim-200-30 gld09648 0.1 63.6 67.6 4 0.1 0.05 1.8 1 (2.15) 17.55 0.1 (2.45) 100 0.1 2.7 (1.5) 0.1 11.4 47.4 0.1 4 0.1 101 200 1 0.1 0.1 2.4 (1.8) (2.45) (2.15) 2 min. 6 0.1 0.1 20 burnished, no burr allowed -0.18 0.25 2.55 detail of contacts 3.8 max. 30 0.1 1 0.15 0.03 0.45 0.6 0.1
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram package outlines data sheet 45 rev. 0.91, 2004-06 09122003-ftxn-km26 figure 6 package outline l-dim-200-31 gld09649 0.1 63.6 67.6 4 0.1 0.05 1.8 1 (2.15) 17.55 0.1 (2.45) 100 0.1 2.7 (1.5) 0.1 11.4 47.4 0.1 4 0.1 101 200 1 0.1 0.1 2.4 (1.8) (2.45) (2.15) 2 min. 6 0.1 0.1 20 burnished, no burr allowed -0.18 0.25 2.55 detail of contacts 3.8 max. 30 0.1 1 0.15 0.03 0.45 0.6 0.1
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram package outlines data sheet 46 rev. 0.91, 2004-06 09122003-ftxn-km26 figure 7 package outline l-dim-200-33 detail of chamfer 0.2 - 0.15 0.2 - 0.15 3.8 max. 1 0. 1 67.6 63.6 30.00 2.15 11.4 1 39 41 199 47.4 4.2 0.15 0.13 2.45 20 2.45 1.8 4 6 240 42 200 1.0 4 2.15 2.55 0.25 0.6 detail of contacts 0.45 2.7
hys64t[32000/64020/128021][g/h]dl?[3.7/5]?a 512 mbit ddr2 sdram product type nomenclature (ddr2 drams and dimms) data sheet 47 rev. 0.91, 2004-06 09122003-ftxn-km26 8 product type nomenclature (ddr2 drams and dimms) infineon?s nomenclature uses simple coding combined with some propriatory coding. table 22 provides examples for module and component product type number as well as the field number. the detailed field description together with possible values and coding explanation is listed for modules in table 23 and for components in table 24 . table 22 nomenclature fields and examples example for field number 1234567891011 micro-dimm hys64t64020km?5?a ddr2 dram hyb 18 t 512 16 0 a c ?5 table 23 ddr2 dimm nomenclature field description values coding 1 infineon modul prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3 dram technology tddr2 4 memory density per i/o [mbit]; module density 1) 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 5raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free status a .. z look up table 9 module type s s o-dimm m m icro-dimm r r egistered u u nbuffered 10 speed grade ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 11 die revision ?a first ?b second 1) multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the overall module memory density in mbytes as listed in column ?coding?. table 24 ddr2 dram nomenclature field description values coding 1 infineon component prefix hyb constant 2 interface voltage [v] 18 sstl1.8 3 dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status cfbga, lead-containing f fbga, lead-free 10 speed grade ?3.7 ddr2-533 ?5 ddr2-400 11 n/a for components
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